The invention relates to the manufacture of semiconductor devices. More specifically, the invention relates to the manufacture of dual damascene structures in low-K dielectric material.
Integrated circuits use dielectric layers, which have typically been formed from silicon dioxide, SiO2, to insulate conductive lines on various layers of a semiconductor structure. As semiconductor circuits become faster and more compact, operating frequencies increase and the distances between the conductive lines within the semiconductor device decrease. This introduces an increased level of coupling capacitance to the circuit, which has the drawback of slowing the operation of the semiconductor device. Therefore, it has become important to use dielectric layers that are capable of effectively insulating conductive lines against such increasing coupling capacitance levels.
In general, the coupling capacitance in an integrated circuit is directly proportional to the dielectric constant, K, of the material used to form the dielectric layers. As noted above, the dielectric layers in conventional integrated circuits have traditionally been formed of SiO2, which has a dielectric constant of about 4.0. As a consequence of the increasing line densities and operating frequencies in semiconductor devices, dielectric layers formed of SiO2 may not effectively insulate the conductive lines to the extent required to avoid increased coupling capacitance levels.
In an effort to reduce the coupling capacitance levels in integrated circuits, the semiconductor industry has engaged in research to develop materials having a dielectric constant lower than that of SiO2, which materials are suitable for use in forming the dielectric layers in integrated circuits. To date, a number of promising materials, which are sometimes referred to as xe2x80x9clow-K materialsxe2x80x9d, have been developed.
One interesting class of organic low-K materials is compounds including organosilicate glass. By way of example, but not limitation, such organosilicate dielectrics include CORAL(trademark) from Novellus Systems, Inc. of San Jose, Calif.; Black Diamond(trademark) from Applied Materials of Santa Clara, Calif.; and Sumika Film(copyright) available from Sumitomo Chemical America, Inc., Santa Clara, Calif. Another class of low-K materials would be spin-on glass.
During semiconductor wafer processing, features of the semiconductor device have been defined in the wafer using well-known patterning and etching processes. In these processes, a photoresist material may be deposited on the wafer and may then be exposed to light filtered by a reticle. The reticle may be a glass plate that is patterned with exemplary feature geometries that block light from propagating through the reticle.
During the photoresist layer forming, the photoresist may become nitrogen poisoned. This nitrogen poisoning may cause photoresist to adhere to where it should not be, which may prevent the etching of an area of the low-K dielectric, where etching may be desired. Thus, nitrogen poisoning may prevent proper mask patterning by preventing developed photoresist from being removed.
To facilitate understanding, FIG. 1 is a flow chart of a dual damascene etching process that may be used in the prior art. During such a process, a low-K layer and barrier layer may be formed on a substrate (step 104). FIG. 2 is a cross-sectional view of a barrier layer 202 and a low-K layer 204 on a substrate 208. The substrate may be semiconductor devices or an interconnect layer or other layers. If the substrate 208 is a copper interconnect, the barrier layer 202 may be a silicon carbide layer with added nitrogen to prevent the substrate from copper diffusion into the low-K layer 204. The low-K layer 204 may form an inter layer dielectric. An etch stop layer 212 may be placed within the low-K layer 204. A protective layer 216, such as a modified low-K layer or oxide layer, may be formed on the surface of the low-K layer 204. An anti-reflective coating (ARC) 220 may be formed on the surface of the low-K layer (step 108). The ARC may be a spun-on organic ARC or an inorganic deposited film ARC, such as PEARL(trademark) manufactured by Novellus(trademark). A patterned mask 224 for etching vias is formed over the antireflective coating 220 (step 112). Typically, such a mask is formed with a photoresist material.
The patterned mask is used to etch vias 304, as shown in FIG. 3 (step 116). The via forming mask may then be removed by ashing the via forming mask (step 120). A bottom antireflective coat (BARC) 308 may be formed (step 124) and then etched back (step 128) on the bottom of the via 304. The BARC may typically be an organic spun-on material. A patterned trench mask 404 may then be formed (step 132), as shown in FIG. 4. The desired trench is shown by broken lines 408. However, due to nitrogen poisoning of the photoresist by nitrogen, possibly from the barrier layer or inorganic ARC, photoresist residue 412 over the desired trench adheres to the low-K material and is not removed as desired. The trench is the etched (step 136). The photoresist residue 412 prevents etching of the trench under the residue 412. As a result, only parts of the trench 416 may be etched.
The patterned trench mask 404 may then be removed by ashing (step 140). The substrate may be heated to provide annealing and degassing (step 144 to remove gases and moisture. A barrier layer Copper may be deposited over the barrier layer (step 152) to form conductive interconnects. Chemical mechanical polishing may be used to provide a smooth upper surface (step 156).
Without being limited by theory, it is believed that, for some photoresist, light causes the photoresist to produce a small mount of acid. The small amount of acid may be used as a catalyst to produce more acid, which cause a reaction to form a pattern. The presence of a base material, such as nitrogen, may cause the neutralization of the small amount of acid, which may prevent the generation of more acid, so that the pattern is not developed. As a result, the photoresist may not be removed at the locations desired. Accordingly, nitrogen, which is a component of inorganic ARC and the silicon carbide barrier layer 202, may migrate through the low-K material and through the BARC to the photoresist, which may poison a region of the photoresists and which may prevent parts of the photoresist from properly developing.
To achieve the foregoing and in accordance with the purpose of the present invention, a method for forming a dual damascene interconnect in a dielectric layer is provided. Generally a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.